International Journal of

Automation and Smart Technology

Mohamed Salah Salhi1*, Manel Salhi1, and Hamid Amiri1

1University of Tunis El Manar, National Engineering School of Tunis-Tunisia, Research Laboratory of Signal Image and Information Technology LR-SITI.

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ABSTRACT

This paper presents an accelerated algorithm realized on field programming gate array FPGA to mimic the human vision system.  The FPGA is chosen as support owing to their real time propriety RTP. The proposed approach aims to detect any natural image and obtain a "cyclopean image" that provides information on the objects depth with a better details resolution. This strategy uses the common advantages of hybrid stereo imaging models in processing two images of the same scene captured from different viewing angles. Then, it merges the two views to produce a final image containing the depth information of different objects. The adopted algorithm is applied to obstacles detection in which execution time is experimented and shown in results below.


Keywords: Accelerated algorithm; Stereo imaging models; Cyclopean image; Real time propriety RTP.


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ARTICLE INFORMATION



Accepted: 2023-05-01
Available Online: 2023-05-01


Cite this article:

Salhi, M. S., Salhi, M., and Amiri, H. (2023) Boarding and Acceleration on FPGA of an Obstacle Detection Module over Stereo Image. Int. j. autom. smart technol. https://doi.org/10.5875/ausmt.v13i1.2366

  Copyright The Author(s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.

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