International Journal of Applied Science and Engineering
Published by Chaoyang University of Technology

Kalavathi Devi Ta,* and C Venkateshb

a Senior Lecturer, Department of EEE, Kongu Engineering College, Perundurai, Erode., TN, India
b Dean, Faculty of Engineering, Erode Builders Institute of Technology, Erode., TN, India


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ABSTRACT


In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.


Keywords: wave pipelining; self reset logic; Viterbi decoder; micro wind; and layout.


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REFERENCES


  1. [1] Tsui, C. Y., Cheng, R. S., and Ling, K. 1999. Low power ACS unit design for the Viterbi decoder. Proceedings of the IEEE symposium on Circuits and Systems: 137-140.

  2. [2] Dalia, A. El-Dib and Elmasry, M. I. 2004. Modified Register-Exchange Viterbi Decoder for Low-Power Wireless Communications. IEEE Transactions on Circuits and Systems I: Regular Papers, 51, 2: 371- 378.

  3. [3] Forney, G. 1973. The Viterbi Algorithm. Proceedings of the IEEE.61, 3: 268-278.

  4. [4] Hauck, B. and Huss, B. 1998. Asynchronous wave pipelines for high throughput datapaths. Proc. IEEE International. Conf. on Circuits Syst.1: 283–286.

  5. [5] Lou, H. L. 1995. Implementing the Viterbi Algorithm. IEEE Signal Processing Magazine.

  6. [6] Kong, J. J. and Parhi, K. K. 2004. Low-Latency Architectures For High- Throughput Rate Viterbi Decoders. IEEE Transactions on Very Large Scale Inte-gration Systems, 12, 6.

  7. [7] Litvin, M. E. and Mourad, S. 2005. Self-reset logic for fast arithmetic applications. IEEE transactions on Very Large Scale Integration systems. 13, 4: 462-475.

  8. [8] Litvin, M. and Mourad, S. 2006. Wave Pipelining with self reset Logic. IEEE International Conference on Electronic Circuits and Systems. ICECS Nice, France.

  9. [9] Niko, B. and Elisabeth S. 2004. A 2.8 Gb/s, 32-State, Radix-4 Viterbi Decoder Add-Compare-Select Unit. International symposium on VLSI circuits digest of technical papers. 170-173.

  10. [10] Shao, W. and Brackenbury, L. 2008. Pre-Processing of Convolutional Codes for reducing Decoding Power Consumption. Proceedings of the IEEE.

  11. [11] Jin, J. and Tsui, C. Y. 2007. Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. IEEE Transactions on Very Large Scale Integration (VLSI) systems. 15, 10: 1172-1177.

  12. [12] Goo, Y. J. and Lee, H. 2008. Two Bit-Level Pipelined Viterbi Decoder for High Performance UWB Applications. IEEE International Symposium on Circuits and system. 18-21.

  13. [13] Senthilkumar, A. and Natarajan, A. M. 2008. Design of high speed Asynchronous pipelined FIR Filter using Quasi delay Insensitive reduced Slack Prechared half buffer. International journal of Applied Science and Engineering.6, 2: 181-197.

  14. [14] Proakis, J. G. 2000. Digital Communications. McGraw Hill Higher Education. New Ed. Edition.

  15. [15] Shaker, S. W., Elramly, S. H., and Shehata, K. 2009. Design and implementation of Low Power Viterbi decoder for Software defined Wimax receiver. Proceedings of 17th Telecommunications forum TELFOR, Belgrade: 468-471.


ARTICLE INFORMATION




Accepted: 2010-10-26
Available Online: 2021-01-22


Cite this article:

Devi, T.K., Venkatesh, C. 2010. Wave pipelined VLSI architecture for a viterbi decoder using self reset logic with 0.65nm technology. International Journal of Applied Science and Engineering, 8, 65–75. https://doi.org/10.6703/IJASE.2010.8(1).65


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