International Journal of Applied Science and Engineering
Published by Chaoyang University of Technology

Kiran Kumar V. G.*, Shantharama Rai C.

Department of Electronics and Communication Engineering, A J Institute of Engineering and Technology, Kottara Mangaluru, India


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Internet of things (IoT), being the technology of this generation and several billions of electronic devices exchanging a huge secure information. With the low resource devices like the sensors, RFIDs etc. to the super computers and the clouds the security and privacy issues remain a concern. While the conventional cryptographic algorithms approved by the National Institute of Standards and Technology, could be embedded into the Low-resource devices their performance may be reduced, then the design of Ciphers for such resource constrained devices become a challenge with the security principles confidentiality, Integrity and Availability remains the same.
This paper proposes, simple encryption schemes based on arithmetic operations Addition-Modulo/Multiplication Modulo, Rotation and XOR hence the name ARX/MRX. The cipher schemes have been implemented using reversible logic and Vedic Mathematics. The adders have been implanted using reversible logic and multipliers and the modular algorithms have been implemented using the combination of Vedic maths and Reversible logic. The software and hardware implementations are presented. The Histogram, Correlation coefficient and Entropy are found for the grayscale plaintext image using MATLAB to evaluate the security, and the hardware implementation is done writing Verilog code using Xilinx-Vivado and is verified using Nexys-4 Artix-7 FPGA the performance of the encryption schemes are analysed and compared with the existing literature.

Keywords: Low resource devices, FPGA, Internet of Things, ARX/MRX, Reversible logic.

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  1. Abed, S., Jaffal, R., Mohd, B.J., Alshayeji, M. 2019. FPGA modeling and optimization of a SIMON lightweight block cipher. Sensors, 19, 913.

  2. Acholli, S., Ningappa, K.G. 2019. VLSI implementation of hybrid cryptography algorithm using LFSR key. International Journal of Intelligent Engineering and Systems, 12, 10–19.

  3. Bache, F., Schneider, T., Moradi, A., Giineysu, T. 2017. SPARX-A side-channel protected processor for ARX-based cryptography, Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, 990–995.

  4. Dehnavi, S.M., Rishakani, A.M., Shamsabad, M.M., Maimani, H., Pasha, E. 2016. Cryptographic properties of addition modulo 2n. IACR Cryptology ePrint Archive 181.

  5. Devi, D.I., Chithra, S., Sethumadhavan, M. 2019. Hardware random number generator using FPGA, Journal of Cyber Security and Mobility, 8, 409–418. doi:

  6. Justin, R., Mathew, B.K., Abe, S. 2016. FPGA implementation of high quality random number generator using LUT based shift registers, International Conference on Emerging Trends in Engineering, Science and Technology ICETEST 2015, Science Direct Procedia Technology 24, 1155–1162.

  7. Katagi, M., Moriai, S. 2008. Lightweight cryptography for the internet of things; Sony corporation, 7–10.

  8. Khanam, R., Rahman, A., Pushpam, May, 2017. Review on reversible logic circuits and its application, 2017 International Conference on Computing, Communication and Automation (ICCCA2017), 5–6.

  9. Kumar, V.G.K., Rai, S.C. 2019. Implementation and analysis of cryptographic ciphers in FPGA. In: Abraham A., Dutta, P., Mandal, J., Bhattacharya, A., Dutta, S. (eds) Emerging Technologies in Data Mining and Information Security. Advances in Intelligent Systems and Computing, 755. Springer, Singapore.

  10. Li, S., Song, H., Iqbal, M. 2019. Privacy and security for Resource-constrained IoT devices and networks: Research challenges and opportunities. Sensors, 19, 1935.

  11. McKay, K.A., Bassham, M., Turan, M.S., Mouha, N. 2016. DRAFT NISTIR 8114 report on lightweight cryptography, National Institute of Standards and Technology Internal Report 8114.

  12. Mohd, B.J., Hayajneh, T., Vasilakos, A.V. 2015. A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues. Journal of Network Computer Applications. 58, 73–93.

  13. Patel, S.T. Mistry, N.H. 2015. A survey: lightweight cryptography in WSN, in International Conference on Communication Networks (ICCN). IEEE.

  14. Poojari, A., Nagesh, H.R., Kumar, K.V.G., Rai, S.C. 2020. A novel key scheduling algorithm for lightweight cryptographic applications, International Journal of Advanced Trends in Computer Science and Engineering, 9,

  15. Priyanka, M.P., Prasad, E.L., Reddy, A.R. 2016. FPGA implementation of image encryption and decryption using AES 128-bit core, 2016 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, 1–5.

  16. Rana, S., Hossain, S., Shoun, H.I., Kashem, M.A. 2018. An effective lightweight cryptographic algorithm to secure resource-constrained devices, International Journal of Advanced Computer Science and Applications (IJACSA) 9.

  17. Sruthi, N., Nandakumar, R., Rajkumar, P. 2016. Design and characterization of HIGHT cryptocore, 2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), Paralakhemundi, 205-209.

  18. Teh, J.S., Teng, W., Samsudin, A., Chen, J. 2020. A post-processing method for true random number generators based on hyperchaos with applications in audio-based generators. Front. Comput. Sci. 14, 146405.

  19. Usman, M., Ahmed, I., Aslam, M.I., Khan, S., Shah, U.A. 2017. SIT: A lightweight encryption algorithm for secure internet of things. International Journal of Advanced Computer Science and Applications(ijacsa), 8,

  20. Vergos, H.T., Efstathiou, C., Nikolos, D. 2002. Diminished-one modulo 2n + 1 adder design, IEEE Transactions on Computers, 51, 1389–1399.

  21. Vishwakarma, P.P., Tripathy, A.K., Vemuru, S. 2020. Designing a cryptosystem for data at rest encryption in mobile payments. International Journal of Applied Science and Engineering, 17, 373–382.

  22. Wang, Z., Jullien, G.A., Miller, W.C. An algorithm for multiplication modulo (2^N-1), ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set), 956.

  23. Weber, M., Boban, M. 2016. Security challenges of the internet of things, 2016 39th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), Opatija, Croatia, 638–643, doi: 10.1109/MIPRO.2016.7522219.

  24. Zhang, X. 2011. Reversible data hiding in encrypted image, in IEEE Signal Processing Letters, 18, 255–258, doi: 10.1109/LSP.2011.2114651.

  25. Zhang, X. 2012. Separable reversible data hiding in encrypted image, in IEEE Transactions on Information Forensics and Security, 7, 826–832, doi: 10.1109/ TIFS.2011.2176120.

  26. Zimmermann, R. Apr. 1999. Efficient VLSI implementation of modulo 2 n ±1 addition and multiplication, Proc. 14th IEEE Symposium on Computer Arithmetic, 158–167.


Received: 2020-09-05

Accepted: 2020-12-12
Available Online: 2021-06-01

Cite this article:

Kumar, V.G.K., Rai, S.C. 2021. FPGA implementation of a lightweight simple encryption scheme to secure IoT using novel key scheduling technique, International Journal of Applied Science and Engineering, 18, 2020153.

  Copyright The Author(s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.

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